1. Field
The present embodiments relate to a method, system, and program for supporting different storage interconnect architectures and transport protocols at an adaptor.
2. Description of the Related Art
An adaptor or multi-channel protocol controller enables a device coupled to the adaptor to communicate with one or more connected end devices according to a storage interconnect architecture, also known as a hardware interface, where a storage interconnect architecture defines a standard way to communicate and recognize such communications, such as Serial Attached Small Computer System Interface (SCSI) (SAS), Serial Advanced Technology Attachment (SATA), Fibre Channel, etc. These storage interconnect architectures allow a device to maintain one or more connections to another end device via a point-to-point connection, an arbitrated loop of devices, an expander providing a connection to further end devices, or a fabric comprising interconnected switches providing connections to multiple end devices. In the SAS/SATA architecture, a SAS port is comprised of one or more SAS PHYs, where each SAS PHY interfaces a physical layer, i.e., the physical interface or connection, and a SAS link layer having multiple protocol link layer. Communications from the SAS PHYs in a port are processed by the transport layers for that port. There is one transport layer for each SAS port to interface with each type of application layer supported by the port. A “PHY” as defined in the SAS protocol is a device object that is used to interface to other devices and a physical interface. Further details on the SAS architecture for devices and expanders is described in the technology specification “Information Technology—Serial Attached SCSI (SAS)”, reference no. ISO/IEC 14776-150:200x and ANSI INCITS.***:200x PHY layer (Jul. 9, 2003), published by ANSI; details on the Fibre Channel architecture are described in the technology specification “Fibre Channel Framing and Signaling Interface”, document no. ISO/IEC AWI 14165-25; details on the SATA architecture are described in the technology specification “Serial ATA: High Speed Serialized AT Attachment” Rev. 1.0A (January 2003).
Within an adaptor, the PHY layer performs the serial to parallel conversion of data, so that parallel data is transmitted to layers above the PHY layer, and serial data is transmitted from the PHY layer through the physical interface to the PHY layer of a receiving device. In the SAS specification, there is one set of link layers for each SAS PHY layer, so that effectively each link layer protocol engine is coupled to a parallel-to-serial converter in the PHY layer. A connection path connects to a port coupled to each PHY layer in the adaptor and terminate in a physical interface within another device or on an expander device, where the connection path may comprise a cable or etched paths on a printed circuit board.
An expander is a device that facilitates communication and provides for routing among multiple SAS devices, where multiple SAS devices and additional expanders connect to the ports on the expander, where each port has one or more SAS PHYs and corresponding physical interfaces. The expander also extends the distance of the connection between SAS devices. The expander may route information from a device connecting to a SAS PHY on the expander to another SAS device connecting to the expander PHYs. In SAS, using the expander requires additional serial to parallel conversions in the PHY layers of the expander ports. Upon receiving a frame, a serial-to-parallel converter, which may be part of the PHY, converts the received data from serial to parallel to route internally to an output SAS PHY, which converts the frame from parallel to serial to the target device. The SAS PHY may convert parallel data to serial data through one or more encoders and convert serial data to parallel data through a parallel data builder and one or more decoders. A phased lock loop (PLL) may be used to track incoming serial data and lock into the frequency and phase of the signal. This tracking of the signal may introduce noise and error into the signal.